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3 v lvds quad cmos differential line receiver adn4668 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features 15 kv esd protection on receiver input pins 400 mbps (200 mhz) switching rates flow-through pin configuration simplifies pcb layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.3 v power supply high impedance outputs on power-down low power design (3 mw quiescent typical) interoperable with existing 5 v lvds drivers accepts small swing (310 mv typical) differential input signal levels supports open, short, and terminated input fail-safe 0 v to ?100 mv threshold region conforms to tia/eia-644 lvds standard industrial operating temperature range of ?40c to +85c available in 16-lead surface-mount soic and 16-lead low profile tssop package applications point-to-point data transmission multidrop buses clock distribution networks backplane receivers functional block diagram r1 r2 r3 r4 r in1+ v cc gnd adn4668 r in1? r in2+ r in2? r in3+ r in3? r in4+ r out1 r out2 r out3 r out4 r in4? en en 07237-001 figure 1. general description the adn4668 is a quad-channel cmos, low voltage differential signaling (lvds) line receiver offering data rates of over 400 mbps (200 mhz) and ultralow power consumption. it features a flow- through pin configuration for easy pcb layout and separation of input and output signals. the device accepts low voltage (310 mv typical) differential input signals and converts them to a single-ended, 3 v ttl/cmos logic level. the adn4668 also offers active-high and active-low enable/disable inputs (en and en ) that control all four receivers. they disable the receivers and switch the outputs to a high impedance state. this high impedance state allows the outputs of one or more adn4668s to be multiplexed together and reduces the quies- cent power consumption to 3 mw typical. the adn4668 and its companion driver, the adn4667, offer a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ecl) or positive emitter-coupled logic (pecl).
adn4668 rev. a | page 2 of 12 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ac characteristics ........................................................................ 4 ? test circuits and waveforms ...................................................... 4 ? absolute maximum ratings ............................................................ 6 ? esd caution...................................................................................6 ? pin configuration and function descriptions ..............................7 ? typical performance characteristics ..............................................8 ? theory of operation ...................................................................... 11 ? enable inputs .............................................................................. 11 ? applications information .......................................................... 11 ? outline dimensions ....................................................................... 12 ? ordering guide .......................................................................... 12 ? revision history 7/08rev. 0 to rev. a added 16-lead soic_n .................................................... universal changes to table 1 ............................................................................ 3 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 12 3/08revision 0: initial version
adn4668 rev. a | page 3 of 12 specifications v dd = 3.0 v to 3.6 v, c l = 15 pf to gnd, all specifications t min to t max , unless otherwise noted. 1 , 2 table 1. parameter min typ max unit conditions/comments lvds inputs (r inx+ , r inx? ) differential input high threshold, v th at r inx+ , r inx? 3 ?35 0 mv v cm = 1.2 v, 0.05 v, 2.95 v differential input low threshold, v tl at r inx+ , r inx? 3 ?100 ?35 mv v cm = 1.2 v, 0.05 v, 2.95 v common-mode voltage range, v cmr at r inx+ , r inx? 4 0.1 2.3 v v id = 200 mv p-p input current, i in at r inx+ , r inx? ?10 5 +10 a v in = 2.8 v, v cc = 3.6 v or 0 v ?10 1 +10 a v in = 0 v, v cc = 3.6 v or 0 v ?20 1 +20 a v in = 3.6 v, v cc = 0 v logic inputs input high voltage, v ih 2.0 v cc v input low voltage, v il gnd 0.8 v input current, i in ?10 5 +10 a v in = 0 v or v cc , other input = v cc or gnd input clamp voltage, v cl ?1.5 ?0.8 v i cl = ?18 ma outputs (r outx ) output high voltage, v oh 2.7 3.3 v i oh = ?0.4 ma, v id = 200 mv 2.7 3.3 v i oh = ?0.4 ma, input terminated 2.7 3.3 v i oh = ?0.4 ma, input shorted output low voltage, v ol 0.05 0.25 v i ol = 2 ma, v id = ?200 mv output short-circuit current, i os 5 ?15 ?47 ?100 v enabled, v out = 0 v output off state current, i oz ?10 1 +10 a disabled, v out = 0 v or v cc power supply no load supply, current receivers enabled, i cc 12 15 ma en = v cc , inputs open no load supply, current receivers disabled, i ccz 1 5 ma en = gnd, inputs open esd protection r inx+ , r inx? pins 15 kv human body model all pins except r inx+ , r inx? 3.5 kv human body model 1 current-into-device pins are defined as positive. current-out-of-de vice pins are defined as negative. all voltages are referen ced to ground, unless otherwise specified. 2 all typicals are given for v cc = 3.3 v and t a = 25c. 3 v cc is always higher than the r inx+ and r inx? voltage. r inx? and r inx+ have a voltage range of ?0.2 v to v cc ? v id /2. however, to be compliant with ac specifications, the common voltage range is 0.1 v to 2.3 v. 4 v cmr is reduced for larger v id . for example, if v id = 400 mv, v cmr is 0.2 v to 2.2 v. the fail-safe condition with inputs shorted is not supported over the common-mode range of 0 v to 2.4 v but is supported only with inputs shorted and no external common-mode voltage applied. v id up to v cc ? 0 v can be applied to the r inx+ /r inx? inputs with the common-mode voltage set to v cc /2. propagation delay and differential pulse skew decrease when v id is increased from 200 mv to 400 mv. skew specifications apply for 200 mv v id 800 mv over the common-mode range. 5 output short-circuit current (i os ) is specified as magnitude only; a minus sign indicates direction only. only one output should be shorted at a time; do not ex ceed the maximum junction temperature specification.
adn4668 rev. a | page 4 of 12 ac characteristics v dd = 3.0 v to 3.6 v, c l = 15 pf to gnd, all specifications t min to t max , unless otherwise noted. 1 , 2 , 3 , 4 table 2. parameter 5 min typ max unit conditions/comments 6 differential propagation delay, high-to-low, t phld 1.2 2.0 2.7 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 differential propagation delay, low-to-high, t plhd 1.2 1.9 2.7 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 differential pulse skew |t phld ? t plhd |, t skd1 8 0 0.1 0.4 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 differential channel-to-channel skew, same device, t skd2 3 0 0.15 0.5 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 differential part-to-part skew, t skd3 4 1.0 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 differential part-to-part skew, t skd4 9 1.5 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 rise time, t tlh 0.5 1.0 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 fall time, t thl 0.35 1.0 ns c l = 15 pf, 7 v id = 200 mv, see figure 2 and figure 3 disable time, high-to-z, t phz 8 14 ns r l = 2 k, c l = 15 pf, 7 see figure 4 and figure 5 disable time, low-to-z, t plz 8 14 ns r l = 2 k, c l = 15 pf, 7 see figure 4 and figure 5 enable time, z-to-high, t pzh 9 14 ns r l = 2 k, c l = 15 pf, 7 see figure 4 and figure 5 enable time, z-to-low, t pzl 9 14 ns r l = 2 k, c l = 15 pf, 7 see figure 4 and figure 5 maximum operating frequency, f max 10 200 250 mhz all channels switching 1 all typicals are given for v cc = 3.3 v and t a = 25c. 2 generator waveform for all tests, unless otherwise specified: f = 1 mhz, z o = 50 , and t r and t f (0% to 100%) 3 ns for r inx+ /r inx? . 3 channel-to-channel skew, t skd2 , is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any ev ent on the inputs. 4 part-to-part skew, t skd3 , is the differential channel-to-channel skew of any event between devices. this specification applies to devices at the same v cc and within 5c of each other within the operating temperature range. 5 ac parameters are guaranteed by design and characterization. 6 current-into-device pins are defined as positive. current-out-of-de vice pins are defined as negative. all voltages are referen ced to ground, unless otherwise specified. 7 c l includes probe and jig capacitance. 8 t skd1 is the magnitude difference in the differ ential propagation delay time between the positive-going edge and the negative-going edge of the same channel. 9 part-to-part skew, t skd4 , is the differential channel-to-channel skew of any event between devices. this specification applies to devices over the reco mmended operating temperature and voltage ranges and across process distribution. t skd4 is defined as |maximum ? minimum| differential propagation delay. 10 f max generator input conditions: f = 200 mhz, t r = t f < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 v p-p to 1.35 v p-p). output criteria: 60%/40% duty cycle, v ol (maximum = 0.4 v), v oh (minimum = 2.7 v), c l = 15 pf (stray plus probes). test circuits and waveforms signal generator receiver is enabled r inx+ r inx? c l c l = load and test jig capacitance v cc r outx 50? 50? 80% 80% 20% 1.5v 20% 1.5v t plhd t phld r inx? r inx+ 0v (differential) t tlh t thl v oh v ol 1.2v 1.3v 1.1v r outx v id = 200mv 07237-003 figure 3. receiver propagation delay and transition time waveforms
adn4668 rev. a | page 5 of 12 r outx r inx+ 50? c l en en signal generator r inx? v cc gnd s1 notes 1. c l includes load and test jig capacitance. 2. s1 connected to v cc for t pzl and t plz measurements. 3. s1 connected to gnd for t pzh and t phz measurements. r l 07237-004 figure 4. test circuit for receiver enable/disable delay 3v 0v 3 v 0v t plz t phz t pzh t pzl v oh gnd v ol v cc en with en = gnd or open circuit en with en = v cc 50% 50% r outx with v id = ?100mv r outx with v id = +100mv 0.5v 1.5v 1.5v 0.5v 07237-005 1.5v 1.5v figure 5. receiver enable/disable delay waveforms
adn4668 rev. a | page 6 of 12 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v cc to gnd ?0.3 v to +4 v input voltage (r inx+ , r inx? ) to gnd ?0.3 v to v cc + 0.3 v enable input voltage (en, en ) to gnd ?0.3 v to v cc + 0.3 v output voltage (r outx ) to gnd ?0.3 v to v cc + 0.3 v operating temperature range industrial ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max ) 150c power dissipation (t j max ? t a )/ ja thermal impedance, ja tssop package 150.4c/w soic package 125c/w 5c reflow soldering peak temperature pb-free 260c 5c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adn4668 rev. a | page 7 of 12 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 r in1+ r in2+ r in2? r in4+ r in3+ r in3? r in1? r in4? 16 15 14 13 12 11 10 9 r out1 r out2 v cc r out4 en r out3 gnd en adn4668 top view (not to scale) 07237-006 figure 6. pin configuration table 4. pin function descriptions pin o. neonic description 1 r in1? receiver channel 1 inverting input. when this input is more negative than r in1+ , r out1 is high. when this input is more positive than r in1+ , r out1 is low. 2 r in1+ receiver channel 1 noninverting input. wh en this input is more positive than r in1? , r out1 is high. when this input is more negative than r in1? , r out1 is low. 3 r in2+ receiver channel 2 noninverting input. wh en this input is more positive than r in2? , r out2 is high. when this input is more negative than r in2? , r out2 is low. 4 r in2? receiver channel 2 inverting input. when this input is more negative than r in2+ , r out2 is high. when this input is more positive than r in2+ , r out2 is low. 5 r in3? receiver channel 3 inverting input. when this input is more negative than r in3+ , r out3 is high. when this input is more positive than r in3+ , r out3 is low. 6 r in3+ receiver channel 3 noninverting input. wh en this input is more positive than r in3? , r out3 is high. when this input is more negative than r in3? , r out3 is low. 7 r in4+ receiver channel 4 noninverting input. wh en this input is more positive than r in4? , r out4 is high. when this input is more negative than r in4? , r out4 is low. 8 r in4? receiver channel 4 inverting input. when this input is more negative than r in4+ , r out4 is high. when this input is more positive than r in4+ , r out4 is low. 9 en active-low enable and power-down input with pull- down (3 v ttl/cmos). when en is held high, en enables the receiver outputs when en is low or open circuit and puts the receiv er outputs into a high impedance state and powers down the device when en is high. 10 r out4 receiver channel 4 output (3 v ttl/cmos). if the differential input voltage between r in4+ and r in4? is positive, this output is high. if the differ ential input voltage is nega tive, this output is low. 11 r out3 receiver channel 3 output (3 v ttl/cmos). if the differential input voltage between r in3+ and r in3? is positive, this output is high. if the differ ential input voltage is nega tive, this output is low. 12 gnd ground reference point for all circuitry on the part. 13 v cc power supply input. these parts can be operated from 3.0 v to 3.6 v. 14 r out2 receiver channel 2 output (3 v ttl/cmos). if the differential input voltage between r in2+ and r in2? is positive, this output is high. if the differ ential input voltage is nega tive, this output is low. 15 r out1 receiver channel 1 output (3 v ttl/cmos). if the differential input voltage between r in1+ and r in1? is positive, this output is high. if the differ ential input voltage is nega tive, this output is low. 16 en active-high enable and power-down input (3 v ttl/cmos). when en is held low or open circuit, en enables the receiver outputs when en is high an d puts the receiver outputs into a high impedance state and powers down the device when en is low.
adn4668 rev. a | page 8 of 12 typical performance characteristics 3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output high voltage, v oh (v) power supply voltage, v cc (v) i load = ?400a t a = 25c v id = 200mv 07237-007 figure 7. output high voltage, v oh vs. power supply voltage, v cc 33.60 33.55 33.50 33.45 33.40 33.35 33.30 33.25 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output low voltage, v ol (mv) power supply voltage, v cc (v) i load = 2a t a = 25c v id = ?200mv 07237-008 figure 8. output low voltage, v ol vs. power supply voltage, v cc ? 35 ?37 ?39 ?41 ?43 ?45 ?47 ?49 ?51 ?53 ?55 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output short-circuit current, i os (ma) power supply voltage, v cc (v) 07237-009 v out = 0v t a = 25c figure 9. output short-circuit current, i os vs. power supply voltage, v cc ? 0.06 ?0.07 ?0.08 ?0.09 ?0.10 ?0.11 ?0.12 ?0.13 ?0.14 ?0.15 3.0 3.1 3.2 3.3 3.4 3.5 3.6 output tristate current, i os (na) power supply voltage, v cc (v) 07237-010 v out = 0v t a = 25c figure 10. output tristate current, i os vs. power supply voltage, v cc 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 3.0 3.1 3.2 3.3 3.4 3.5 3.6 threshold voltage, v th (mv) power supply voltage, v cc (v) 07237-011 v out = 0v t a = 25c figure 11. threshold voltage, v th vs. power supply voltage, v cc 100 90 80 70 60 50 40 30 20 10 0 10k 100k 1m 10m 100m 1g power supply current, i cc (ma) bit rate (bps) 07237-012 all channels switching one channel switching figure 12. power supply current, i cc vs. bit rate
adn4668 rev. a | page 9 of 12 93.5 93.0 92.5 92.0 91.5 91.0 90.5 90.0 ?40 ?15 10 35 60 85 07237-022 power supply current, i cc (ma) ambient temperature, t a (c) v cc = 3.3v v id =200mv freq = 200mhz all channels switching figure 13. power supply current, i cc vs. ambient temperature, t a 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 ?40 ?15 10 35 85 60 07237-014 ambient temperature, t a (c) differential propagation delay, t plhd , t phld (ns) t phld t plhd v cc = 3.3v v id =200mv freq = 200mhz c l =15pf figure 14. differential propagation delay, t plhd , t phld vs. ambient temperature, t a 4.0 3.5 3.0 2.5 2.0 1.5 0 0.5 1.0 1.5 3.0 2.0 2.5 07237-015 common-mode voltage, v cm (v) differential propagation delay, t plhd , t phld (ns) t a = 25c freq = 200mhz v id =200mv c l =15pf t phld t plhd figure 15. differential propagation delay, t plhd , t phld vs. common-mode voltage, v cm 2.40 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 3.03.13.23.3 3 3.4 .6 3.5 07237-016 power supply voltage, v cc (v) differential propagation delay, t plhd , t phld (ns) t phld t plhd t a = 25c v id =200mv freq = 200mhz c l =15pf figure 16. differential propagation delay, t plhd , t phld vs. power supply voltage, v cc 8 7 6 5 4 3 2 1 0 0 500 1000 1500 3000 2000 2500 07237-017 differential input voltage, v id (mv) differential propagation delay, t plhd , t phld (ns) t a = 25c freq = 200mhz v cm = 1.2v c l =15pf t phld t plhd figure 17. differential propagation delay, t plhd , t phld vs. differential input voltage, v id 200 150 100 50 0 ?50 ?100 ?150 ?200 3.0 3.1 3.2 3.3 3.4 3.5 3.6 07237-018 differential skew, t skd (ps) power supply voltage, v cc (v) t a =25c v id =200mv freq = 200mhz c l =15pf figure 18. differential skew, t skd vs. power supply voltage, v cc
adn4668 rev. a | page 10 of 12 80 60 40 20 0 ?20 ?40 ?60 ?80 ?40 ?15 10 35 60 85 07237-019 differential skew, t skd (ps) ambient temperature, t a (c) v cc = 3.3v v id =200mv freq = 200mhz c l =15pf 560 550 540 530 520 510 500 490 480 470 460 450 ?40 ?15 10 35 60 80 07237-021 ambient temperature, t a (c) transition time, t tlh , t thl (ps) t thl t tlh v cc = 3.3v v id = 200mv freq = 25mhz c l =15pf figure 19. differential skew, t skd vs. ambient temperature, t a figure 21. transition time, t tlh , t thl vs. ambient temperature, t a 550 540 530 520 510 500 490 480 470 460 3.03.13.23.3 3. 3.4 6 3.5 07237-020 power supply voltage, v cc (v) transition time, t tlh , t thl (ps) t a = 25c v id = 200mv freq = 25mhz c l =15pf t thl t tlh figure 20. transition time, t tlh , t thl vs. power supply voltage, v cc
adn4668 rev. a | page 11 of 12 theory of operation the adn4668 is a quad-channel line receiver for low voltage differential signaling. it takes a differential input signal of 310 mv typical and converts it into a single-ended 3 v ttl/ cmos logic signal. a differential current input signal, received via a transmission medium such as a twisted pair cable, develops a voltage across a terminating resistor, r t . this resistor is chosen to match the characteristic impedance of the medium, typically around 100 . the differential voltage is detected by the receiver and converted back into a single-ended logic signal. when the noninverting receiver input, r inx+ , is positive with respect to the inverting input, r inx? (current flows through r t from r inx+ to r inx? ), r outx is high. when the noninverting receiver input, r in+ , is negative with respect to the inverting input, r inx? (current flows through r t from r inx? to r inx+ ), r outx is low. using the adn4667 as a driver, the received differential current is between 2.5 ma and 4.5 ma (3.1 ma typical), developing between 250 mv and 450 mv across a 100 termination resistor. the received voltage is centered on the receiver offset of 1.2 v. the noninverting receiver input is typically (1.2 v + [310 mv/2]) = 1.355 v, and the inverting receiver input is (1.2 v ? [310 mv/2]) = 1.045 v for logic 1. for logic 0, the inverting and noninverting input voltages are reversed. note that because the differential voltage reverses polarity, the peak-to- peak voltage swing across r t is twice the differential voltage. current-mode signaling offers considerable advantages over voltage-mode signaling, such as the rs-422. the operating current remains fairly constant with increased switching frequency, whereas the operating current of voltage-mode drivers increases exponentially in most cases. this increase is caused by the overlap as internal gates switch between high and low, causing currents to flow from v cc to ground. a current- mode device reverses a constant current between its two outputs, with no significant overlap currents. this is similar to emitter-coupled logic (ecl) and positive emitter- coupled logic (pecl), but without the high quiescent current of ecl and pecl. enable inputs the adn4668 has active-high and active-low enable inputs that put all the logic outputs into a high impedance state when disabled, reducing device current consumption from 9 ma typical to 1 ma typical. see table 5 for a truth table of the enable inputs. table 5. enable inputs truth table en en r inx+ r inx? r outx high low or open 1.045 v 1.355 v 0 high low or open 1.355 v 1.045 v 1 any other combination of en and en x x high-z applications information figure 22 shows a typical application for point-to-point data transmission using the adn4667 as the driver and the adn4668 as the receiver. 07237-023 d in d out r t 100 ?
adn4668 rev. a | page 12 of 12 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 23. 16-lead standard small outline package [soic_n] (r-16) dimensions shown in millimeters and (inches) 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 24 . 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters ordering guide model temperature range packag e description package option adn4668arz 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 ADN4668ARZ-REEL7 1 ?40c to +85c 16-lead standard small outline package [soic_n] r-16 adn4668aruz 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 adn4668aruz-reel7 1 ?40c to +85c 16-lead thin shrink small outline package [tssop] ru-16 1 z = rohs compliant part. ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07237-0-7/08(a)

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